Clock networks, which are also known as clock trees, are used in integrated circuits to distribute clock signals. More particularly, in conventional clock networks, input clock signals are received through dedicated clock input pins. The clock signals are then distributed throughout the integrated circuit using a network of conductors and buffers. Clock networks typically include multiple layers of buffers to improve clock signal integrity.
Applications for integrated circuits often use clock signals that are provided to circuit elements in both halves of an integrated circuit. For example, an application of the optical transport network (OTN) 4 standard uses a high-speed serial interface (HSSI) on an integrated circuit to reach 21 clock signals concurrently that have access to the core circuitry of the integrated circuit. Some or all of these clock signals may need to be provided to circuit elements in both halves of the integrated circuit.
The Stratix® IV GX field programmable gate array (FPGA) integrated circuit designed by Altera Corporation of San Jose, Calif., includes global clock signals, quadrant clock signals, and regional clock signals. The Stratix IV GX FPGA includes numerous programmable logic circuits that are grouped into 4 quadrants on the integrated circuit.
Clock multiplexers near the four edges of the FPGA provide global clock signals to the 4 quadrants of programmable logic circuits on the FPGA. Clock multiplexers near the right and left sides of the FPGA provide global and quadrant clock signals from high-speed serial interfaces (HSSI) on the right and left sides of the FPGA, respectively, to the programmable logic circuits. Each of the quadrant clock signals is provided to only one quadrant of programmable logic circuits.
First and second sets of the regional clock signals are provided from a high-speed serial interface (HSSI) on the left side of the FPGA to first and second quadrants, respectively, of programmable logic circuits on the left side of the FPGA. Third and fourth sets of the regional clock signals are provided from an HSSI on the right side of the FPGA to third and fourth quadrants, respectively, of programmable logic circuits on the right side of the FPGA. Each of the regional clock signals is only provided to ⅛ of the core of programmable logic circuits on the FPGA.
The programmable interconnect conductors in the Stratix IV GX FPGA can be configured to provide a clock signal from a programmable logic circuit in one quadrant of the FPGA to one of the clock multiplexers near that quadrant. One of the clock multiplexers can be configured to drive a clock signal received from a programmable logic circuit as a global clock signal. One of the clock multiplexers can be configured to drive a clock signal received from a programmable logic circuit as a quadrant clock signal. However, the programmable interconnect conductors that route a clock signal from a programmable logic circuit to one of the clock multiplexers may have different lengths in different user configurations of the FPGA, depending on the path selected to route the clock signal through the programmable interconnect conductors. As a result, the programmable interconnect conductors may introduce an unpredictable amount of delay into the clock signal.